![How To Program A Lattice Cpld Programmer How To Program A Lattice Cpld Programmer](https://hackadaycom.files.wordpress.com/2008/12/cover-450-e1415991543677.jpg?w=646)
Lattice Diamond Programmer offers an easy to use solution for programming all Lattice JTAG-based devices. In addition to FPGAs supported in Lattice Diamond, devices from ispLEVER Classic, PAC-Designers, and iCEcube2 are supported by Programmer when used in standalone mode. An alternative solution is to use a Lattice non-volatile FPGA as an FPGA Loader. JTAG programming interface to the Flash, as well as control of data to the other. Select the project type according to the desired use of VHDL or Verilog.
:: FPGA and CPLD JTAG Programming Software FPGA and CPLD Programming With the increasing popularity of JTAG enabled CPLD and FPGA devices, DebugJet has a built-in software algorithm to support the leading CPLD/FPGA manufacturers worldwide such as Actel, Altera, Lattice Semiconductors and Xilinx. Can execute most common functions such as program, erase, verify and test CPLD/FPGA devices. The device can also execute several programming functions on multiple devices from different manufacturer connected in series to a single JTAG port using a single macro command file. There are two ways to program a CPLD/FPGA device using.
The first is by using a with DebugJet target server application to specify the jedec file and the functions to be executed on the programmable logic device. This method is simple since the user has to write the command file once and then execute it via the.
DebugJet also comes with an application called DebugJet JTAG Tester. This applications is capable of programming CPLD/FPGA devices but the user has to enter the commands manually. This is helpful when testing a new JEDEC file or during a development process. A snapshot of the DebugJet JTAG Tester application is shown below.
Eclipse based IDE Debugger Since DebugJet can handle multiple JTAG devices connected in series in a single JTAG chain, there is no need to have a special JTAG port to support only the CPLD/FPGA devices. One single port can be used to program multiple CPLD/FPGA devices as well as. This can be simply done by identifying the chip position in the JTAG chain and providing this information to the host application. Supports leading CPLD and FPGA manufacturer such as Actel, Altera, Lattice Semiconductors and Xilinx. Supports all JEDEC file formats from major manufacturers. Host applications can program multiple CPLD and FPGA devices from different manufacturers connected to a single JTAG port using a single macro script file. Supports Program, erase, verify and victor testing functions.
Programming of CPLD/FPGA devices can be done within a debug session which comes handy for nonvolatile FPGA devices. Programming functions can be executed via a graphical user interface during development cycles or a script file for manufacturing applications. DebugJet CPLD/FPGA is available for free download from the support section.
Overview Lattice did it right by not making things difficult for customers who desire to program their PLDs or FPGAs with a custom JTAG programming adapter (perhaps even designed onto the customer board). Although the Lattice cable is relatively low cost, there is an even lower cost option available: FTDI FT2232H Mini Module. This tiny module is available for approximately $20 from distributors like Digi-Key and Mouser, and it can be used directly as a programming adapter for Lattice devices (and others) by following the setup described below. JTAG is a 4-wire protocol defined by the IEEE (Std 1149.1-2013). The signals that comprise the Test Access Port (TAP) are TCK, TMS, TDI, and TDO. Various implementations also make use of additional pins for test and programming (i.e., TRST).
Support of these additional signals can be accomplished with the FT2232 device through general purpose I/Os; however, our implementation only makes use of the 4 core signals and ground. A disclaimer it warranted here: use these instructions and the mini module with care and at your own risk. We have been using this module for programming various devices for a long time. However, there are associated risks, such as having the un-enclosed mini module short against something, wiring it improperly, using a faulty card, etc.
However, if you exercise caution, review the mini module & device data sheets, and double check your connections, you should be fine. Note it is our understanding that the mini module will only work with 3.3V targets.
Although there are VIO pins on the mini module connector, these pins do not support a voltage other than 3.3V. Inter-board Connections.
MM Pin # MM Pin Name Target Pin # Target Pin Name CN2-2 GND J10-2 GND CN2-7 AD0 J10-3 CPLDTCK CN2-9 AD2 J10-4 CPLDTDO CN2-10 AD1 J10-5 CPLDTDI CN2-12 AD3 J10-6 CPLDTMS.Connection Notes:. Target board is a Freescale TWR-LS1021A, and its JTAG connector is at J10 (6-pin header). Power (3.3V) is not connected between the target board and mini module (MM).
Connections for MM follow USB-bus powered guidelines. The following additional connections are also required:. CN3-1 is connected to CN3-3, which connects USB power to FTDI voltage regulator input. CN2-1 is connected to CN2-11, which ties V3V3 to VIO on FTDI device. The FT2232H is a two port bridge device and either port can be used for JTAG. Our configuration makes use of bus / port A.
This follows other examples, such as the Lattice ECP5 Versa board design, which directly connects a FT2232H device to its FPGA. Lab Bench Image Shown below is a picture of a mini module connected to the target on our lab bench. The target is a Freescale TWR-LS1021A development board.
The TWR development board utilizes a Lattice CPLD and provides a 6-pin in-line programming header. Lattice Programming Software Configuration If everything is connected properly, then the programmer should work without any issues on Windows machines. Of course, you'll have to let the machine detect and load the appropriate USB and FTDI drivers. Once this is done, perform a detect cable, and you should see something similar to what is depicted in the figure below. We update our site daily with new content related to our open source approach to network security and system design. If you would like to be notified about these changes, then please follow us on and join our. Related articles on this site: Open Source FPGA platform for Network Security & Control.